A computer system utilizes multiple buses to connect various components of the computer system. The buses are physical connections that allow the various components to communicate information (e.g., commands, addresses, and data) throughout the system. Different buses generally support different data bandwidths. For instance, a main memory bus that connects a central processing unit (CPU) to the system memory (e.g., dynamic random-access memory (DRAM)) can support a significantly higher data bandwidth than that supported by an input/output (I/O) bus (e.g., peripheral component interconnect (PCI), PCI-Express, etc.).
Traditionally, co-processors and I/O devices interface to the computer system via the I/O bus. For some I/O or co-processing applications, interfacing to the computer system via the I/O bus provides reasonable performance. However, the lower bandwidths supported by I/O buses often create communication bottlenecks for I/O or co-processing applications that are able to operate at much faster speeds.
Therefore, there exists a need for a system and method for interfacing co-processors or I/O devices in a computer system that provides enhanced I/O capabilities and performance. Particularly, there exists a need for a system and method for interfacing co-processors or I/O devices via the main memory system.